Nvidia Looking for Senior ASIC Design Engineer – Hardware at Santa Clara, California Full Time

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI – the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today.

The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the chip. The clocks team interacts with the floor-planning and back end team to help craft the physical floorplan of the chip. The team explains the programming model to the SW team to come up with an efficient clock programming sequence. The team works with the silicon solution team to triage silicon or programming bugs in the lab.

What you’ll be doing:

As a Clocks team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency clocks.

You should be able to engage with multiple teams and design the GPU or CPU clocks to satisfy all the architectural constraints.

Together with other team members, we deliver clock information to GPU, CPU and SOC verification team, timing and DFT teams. You will use Perl to improve the productivity of the above teams.

Collaborate with Software and product design team to debug GPU or CPU clock silicon bugs in our new products.

Understand and design clocking structures to overcome sub-micron design challenges.

Identify improvements in the current design and propose and implement new ways to improve the efficiency in the GPU/CPU clocking design.

What we need to see:

BS in Electrical Engineering or equivalent experience (MS preferred)

3+ years of relevant work experience.

Ability to thrive in a dynamically changing environment.

Experience in RTL design (Verilog), verification and logic synthesis.

Strong coding skills in Perl or other industry-standard scripting languages.

Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus.

Implementing on-chip clocking networks is a bonus.

With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant people in the world working for us and, due to unprecedented growth, our teams are rapidly growing. Are you passionate about becoming a part of a best-in-class team supporting the latest in GPU and AI technology? If so, we want to hear from you.

The base salary range is 128,000 USD – 258,750 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

You will also be eligible for equity and benefits. NVIDIA accepts applications on an ongoing basis.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.